This invention relates to transmission and reception circuits, and particularly relates to transmission and reception circuits for the achievement of information transfer by means of serial signals between semiconductor integrated circuits each performing internal handling of parallel signals.
A recent tremendous increase in the processing amount of moving-picture data requires a high-speed information transfer between semiconductor integrated circuits mounted on a single printed wiring board. One such example of a high-speed information transfer is a transfer of information between a CPU (central processing unit) and a memory by the use of signals such as data signals, address signals, and other control signals. The unit, at which parallel signals are processed in semiconductor integrated circuits, has been increased year by year, and the width of internal buses is now changing to 64 bits and further to 128 bits.
Japanese Unexamined Laid-Open Application Publication No. 2-310762 shows a technique intended for avoiding the problem of noise resulting from simultaneous switchings of a large number of signals occurring at the time of transmitting parallel signals between semiconductor integrated circuits. In the 2-310762 technique, when a first parallel signal, which has been sent onto the external data bus, is switched to a second parallel signal, the second parallel signal is polarity determined such that the number of bits that change is reduced to less than half the total number of bits and a 1-bit signal relating to the polarity determined is transmitted along with the second parallel signal. This 2-310762 technique makes it possible to constantly hold the number of bits that change at the same time on the bus below half the total bit number.
U.S. Pat. No. 5,572,736 also shows a technique for providing a solution to the aforesaid noise problem occurring in transferring parallel signals, wherein data words are transmitted on the bus in the form of code words. The code words are formulated such that the number of bits of the bus which changes with the transmission of successive code words is minimized. The U.S. Pat. No. 5,572,736 technique performs a parallel signal transmission by the use of a code word generated from a data word and a switching code for designating a data word-into-code word mapping.
However, the parallel signal transmission requires numerous signal lines that have to be laid out in a confined space of the printed wiring borad, therefore imposing practical constraints upon the number of external bus bits for the transmission of parallel signals. If a by-pass technique, in which some signal wires are by-passed, is employed, this prevents the implementation of equal-length wiring, therefore giving rise to the problem that there is produced a difference in delay between signal lines.
To cope with such a problem, it has been considered to employ a serial signal transmission technique serving in place of the foregoing parallel signal transmission technique. A parallel-serial converter is disposed in one semiconductor integrated circuit at the transmission end and a serial-parallel converter is disposed in another semiconductor integrated circuit at the reception end, whereby information transfer can be performed in a serial fashion between the semiconductor integrated circuits. For instance, if parallel-serial conversion and serial-parallel conversion are carried out in units of eight bits, this means that the number of signal lines (i.e. the number of external bus bits) necessary for the transfer of information can be reduced to one eighth. This therefore makes it possible to achieve the provision of equal-length wiring on a printed wiring board with ease.
In the above-described serial signal transmission technique, parallel signals are directly (without modification) converted into serial signals. If internal parallel data (for example, 8-bit internal parallel data of 10101010) is repeatedly transmitted many times, there must always be made bit transitions reciprocating between 1 and 0 in serial signals. Assuming here that M is an integer equal to or greater than 2, the bit transition robability (BTP) at the time of transmitting a serial signal of bits is defined as follow. EQU BTP=m/(M-1)
where the denominator M-1 indicates the number of possible bit transitions and the numerator m indicates the number of bit transitions that have actually occurred. The number m is an integer equal to or greater than 0 and equal to or less than M-1. For example, a serial signal corresponding to the foregoing 8-bit data of 10101010 has a BTP of 7/7=1. Even when code words and switching codes, previously described, are employed, the serial signal also has a BTP of 1 if a code word obtained by mapping is 10101010.
The increase of the serial signal BTP gives rise to various drawbacks. For example, if the clock rate is increased too much for the realization of higher-speed information transfer rates, this results in the following problems. One problem is that there is produced an increase in electric power that is consumed. Another problem is that the effect of reflection due to inductance components of a signal line significantly appears in the waveform of a serial signal, as a result of which the change in the voltage level of the serial signal becomes unable to follow up a bit transition. In other words, the voltage level of serial signals is lowered on the way to move upward to the level of logical 1 or is increased on the way to move downward to the level of logical 0, and signal transmission errors occur. For this reason, conventional techniques fail to provide satisfactory high-speed information transfer rates.